Field-programmable gate arrays (FPGAs) are becoming more promising for high-performance computing (HPC). Unlike fixed hardware specialization, reconfigurability allows FPGAs to be customized for a wide variety of HPC workloads.
This project aimed to understand the feasibility of FPGAs as accelerators for some of the key HPC codes at Lawrence Livermore National Laboratory and to identify application characteristics that can benefit from the reconfigurability of FPGAs. We conducted a detailed performance study of FPGAs using sparse matrix computations and identified key optimization techniques to effectively use FPGA hardware resources. While the final performance result is promising, we identified several key, technical challenges that require further research and development.
Our research leveraged and advanced the Laboratory's core competencies in high-performance computing, simulation, and data science. Our results expand Livermore's capabilities using FPGAs for sparse matrix computations used widely in scientific and engineering code across the Laboratory's programs.
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